1. Field of the Invention
The present invention generally relates to managing noise in a power grid or plane of an electronic device, and more particularly to a method of using decoupling capacitors to reduce noise in an integrated circuit, such as an application specific integrated circuit having rows of random logic macros.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cells types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. A few years ago, pure standard cell designs were typical of many integrated circuits, but today's designs for application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs) contain large blocks of reserved areas for memory arrays, proprietary (IP) blocks, etc. Consequently, placement now often requires the arrangement of logic around these large blocks.
One problem that has arisen in these modern electronic devices relates to noise in the power grid of the device. Substantial noise is generated in an integrated circuit chip as digital electronic functions are interconnected or decoupled. FIG. 1 is an illustration of the voltage droop at a given node in the power grid (Vdd) of a typical row-based, ASIC circuit. An efficient metric to estimate power grid induced noise at a node is the integral of the voltage droop below a user-specified noise ceiling NMH. In the example of FIG. 1, this value is 90% of Vdd, the power supply voltage. The power grid provides the power and ground signals throughout the chip, and these are among the most important signals to control reliably, since supply voltage variations can lead not only to problems related to spurious transitions in some case (particularly when dynamic logic is used), but also to delay variations and timing unpredictability. Even if a reliable supply is provided at an input pin of a chip, it can deteriorate significantly within the chip due to imperfections in the conductors that transmit these signals throughout the chip.
Noise in modern electronic circuits is particularly troublesome as it increases the requirements on the noise margins and other circuit parameters. Noise margins have been greatly reduced in modern designs due to the lowering of supply voltages and the presence of a larger number of potential noise generators. With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequencies, lower supply voltages, and higher power dissipation. These features cause a dramatic increase in the currents being delivered through the on-chip power grid.
One solution to this problem lies in the use of decoupling capacitors. On-chip decoupling capacitors (also referred to as “decaps”), which are intentionally attached to the power grid, can reduce power-supply induced noise. For example, in a 300 MHz CMOS reduced instruction set computing (RISC) microprocessor design, as much as 160 nF of on-chip decoupling capacitance may be added to control power supply noise. In another example, the on-chip decoupling capacitance may be sized at ten times that of the total active circuit switching capacitance. The closer decoupling capacitors can be placed in relation to the noise source (such as a switching transistor), the more effective the decoupling will be, primarily due to a decreased inductance in series with the decoupling capacitance. Decoupling capacitors may be provided underneath devices at the surface of an integrated circuit, or distributed in a carrier of the chip. U.S. Pat. No. 5,587,333 notes that, for ASICs consisting of standard library cells, the most effective decoupling method is to integrate decoupling capacitors in each such cell, since the noise is managed at the source. This approach makes it easier for the designer as well, who does not have to consider decoupling when cells or blocks from such a library are used.
While the use of decaps is well-known in the art, the prior art designs are so complex that it has heretofore been impossible to optimize the placement and sizing of the decaps in any meaningful way. Previous work on decap allocation and optimization has focused on application in full custom design styles. Existing methods for adding decoupling capacitance are heuristic and local and are therefore wasteful in chip area. For example, the article “Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement,” Zhao et al., 15th International Conference on VLSI Design, describes a linear programming technique for allocation of white space for decap use, and a heuristic is proposed to insert additional white space into an existing floorplan.
In light of the shortcomings of these approaches, it would be desirable to devise an improved method of mathematically determining the right amount of decoupling capacitance needed by a design. It would be further advantageous if the solution could address the circuit as a whole, rather than merely on a local level.